In conventional system on chip (SOC) designs, a plurality of voltage-adjusting devices is required to provide different voltages to different power domains.
FIG. 1 illustrates the structure of a conventional voltage-adjusting device. The voltage-adjusting device 1 often includes a reference circuit 11, a comparator 12, a driving unit 13, and a feedback unit 14. The two input terminals of the comparator 12 are connected to the output terminal of the reference circuit 11 and the output terminal of the feedback unit 14, respectively. The output terminal of the comparator 12 is connected to the input terminal of the driving unit 13. The output terminal of the driving unit 13 is connected to the input terminal of the feedback unit 14 and the load unit 2.
FIG. 2 illustrates the circuit diagram of the voltage-adjusting device 1 shown in FIG. 1.
As shown in FIG. 2, the driving unit 13 includes a PMOS transistor M1. The feedback unit 14 includes a plurality of resistors, e.g., R1 and R2, connected in series. The feedback unit 14 divides the voltage applied thereon and sends a divided voltage to the comparator 12 as a feedback voltage Vfb. The comparator 12 compares the feedback voltage Vfb and a reference voltage Vref generated by the reference circuit 11. The result of comparison, generated by the comparator 12 is used to determine whether the driving unit 13 is turned on or turned off. When the feedback voltage Vfb and the reference voltage Vref are different, the comparator 12 controls the driving unit 13 to be turned on and change the feedback voltage Vref. A plurality of feedback processes may be performed until the feedback voltage Vfb and the reference voltage Vref are equal to each other. Then, a stable output voltage Vout may be generated. In practice, the reference voltage Vref and the resistors connected in series may be adjusted to obtain a stable output voltage Vout, where Vout is a predetermined voltage value.
Referring to FIG. 2, according to conventional technology, a power gating 21 is often included in the load unit 2. When the load 22 is not in operation, the power gating 21 disconnects the load 22 from the voltage-adjusting device 1 to reduce leakage current. Specifically, the power gating 21 includes a PMOS transistor M2.
However, the conventional voltage-adjusting device often occupies an undesirably large amount of area on the chip. Each power domain that requires voltage-adjusting functions is disposed with a voltage-adjusting device within. Thus, an undesirably large wafer/chip area is needed to dispose a plurality of voltage-adjusting devices.